Delay-bound guarantee in combined input-output buffered switches
نویسندگان
چکیده
A bstrucrCIOB (Combined Input-Output Buffered) switches with a moderate speedup have been widely considered as the most feasiblesolution for large-capacity switches. In this paper, we adopt the hierarchical link sharing (HLS) algorithm in non-blocking CIOB switches to guarantee delay bound that is independent of the switch size. We also propose a feasible architecture to implement the HLS algorithm in the switch, which can accommodate the packet carried over a 10 G bps line without a speedup requirement. Furthermom, we design a new Serial Comparator to find minimum timestamp values.
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تاریخ انتشار 2000